Claims for Patent: 7,265,009

Summary for Patent: 7,265,009

Title:	HDP-CVD methodology for forming PMD layer
Abstract:	A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering at a reduced a thermal budget including providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process over the at least two overlying semiconductor structures without applying a chucking bias Voltage to hold the semiconductor substrate.
Inventor(s):	Chen; Yao-Hsiang (Hsin-Chu, TW)
Assignee:	Taiwan Semiconductor Manufacturing Co., Ltd. (Hsin-Chu, TW)
Application Number:	11/067,043
Patent Claims:	1. A method of forming an HDP-CVD pre-metal dielectric (PMD) layer comprising the steps of: providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a PMD layer according to an HDP-CVD process on the at least two overlying semiconductor structures without applying a chucking bias Voltage to hold the semiconductor substrate; wherein the step of forming a PMD layer comprises a multi-layer deposition process comprising the steps of: forming a first PMD layer portion according to an HDP-CVD process without applying a chucking bias Voltage to hold the semiconductor substrate; and forming a second PMD layer portion on the first PMD layer portion according to an HDP-CVD process without applying a chucking bias Voltage to hold the semiconductor substrate. 2. The method of claim 1, wherein an RF bias is applied to control the semiconductor substrate deposition temperature. 3. The method of claim 2, wherein the RF bias is applied at a level of less than about 1500 Watts. 4. The method of claim 2, wherein the RF bias is applied at a level of less than about 1000 Watts. 5. The method of claim 1, wherein the first PMD layer portion is deposited at a lower deposition/sputter (D/S) ratio compared to the second PMD layer portion. 6. The method of claim 1, wherein the first PMD layer portion is deposited at a higher RF bias compared to the second PMD layer portion. 7. The method of claim 1, wherein the PMD layer is selected from the group consisting of PSG, BPSG, and USG. 8. The method of claim 1, wherein the PMD layer comprises PSG. 9. The method of claim 1, wherein the semiconductor structures comprise CMOS transistors. 10. The method of claim 1, wherein the semiconductor structures comprise an overlying contact etch stop layer. 11. The method of claim 10, wherein the contact etch stop layer is formed having a stress selected from the group consisting of compressive and tensile stress. 12. A method of forming an HDP-CVD pre-metal dielectric (PMD) layer to reduce plasma damage and/or preferential sputtering comprising the steps of: providing a semiconductor substrate comprising CMOS transistor structures separated by a gap; forming a PMD layer on the CMOS transistor structures according to a multi-layer HDP-CVD process comprising depositing a first PMD portion and depositing a second PMD portion wherein an RF bias is adjusted to control a deposition temperature of the semiconductor substrate in the absence of a chucking bias Voltage applied to the semiconductor substrate; and wherein the CMOS transistor structures comprise an overlying contact etch stop layer (CESL). 13. The method of claim 12, wherein the RF bias is applied at a level of less than about 1500 Watts. 14. The method of claim 12, wherein the RF bias is applied at a level of less than about 1000 Watts. 15. The method of claim 12, wherein a first PMD portion is deposited to a level higher than the semiconductor structures followed by deposition of a second PMD portion. 16. The method of claim 12, wherein the first PMD portion is deposited at a lower deposition/sputter (D/S) ratio compared to the second PMD portion. 17. The method of claim 12, wherein the first PMD portion is deposited at a higher RF bias compared to the second PMD portion. 18. The method of claim 12, wherein the PMD layer is selected from the group consisting of PSG, BPSG, and USG. 19. The method of claim 12, wherein the PMD layer comprises PSG. 20. The method of claim 12, wherein the (CESL) is formed having a stress selected from the group consisting of compressive and tensile stress. 21. A method of forming an HDP-CVD pre-metal dielectric (PMD) layer comprising the steps of: providing a semiconductor substrate comprising at least two overlying semiconductor structures separated by a gap; forming a contact etch stop layer on the semiconductor structures, said contact etch stop layer having a stress selected from the group consisting of compressive and tensile stress; and, forming a PMD layer according to a multi-step HDP-CVD process over the contact etch stop layer without applying a chucking bias Voltage to hold the semiconductor substrate. 22. The method of claim 21, wherein the multi-step HDP-CVD process comprises depositing a first PMD layer portion to a level higher than the semiconductor structures followed by deposition of a second PMD layer portion. 23. The method of claim 21, wherein the multi-step HDP-CVD process comprises depositing a first PMD layer portion at a higher RF bias compared to a second PMD layer portion. 24. The method of claim 21, wherein the multi-step HDP-CVD process comprises depositing a first PMD layer portion at a higher semiconductor substrate temperature compared to a second PMD layer portion. 25. The method of claim 1, wherein the first PMD layer portion is deposited to a level higher than the semiconductor structures followed by deposition of the second PMD layer portion. 26. The method of claim 1, wherein the first PMD layer portion is deposited at a higher semiconductor substrate temperature compared to the second PMD layer portion. 27. The method of claim 12, wherein the first PMD portion is deposited at a higher semiconductor substrate temperature compared to the second PMD portion.