Claims for Patent: 5,428,522

Summary for Patent: 5,428,522

Title:	Four quadrant unipolar pulse width modulated inverter
Abstract:	A four quadrant unipolar pulse width modulated (PWM) power conversion circuit for supplying a desired current to an inductive load uses an H-bridge circuit topology with an upper and lower pair of switching elements including a diode in parallel with each of the switching elements to provide a current path from the load to the power source when its respective switching element is non-conductive. A control algorithm generates switching element control signals to cause the instantaneous voltage across the load to alternate between a single polarity voltage and zero for a portion of the output load waveform to cause the average value of the load current to correspond generally with the desired average load current.
Inventor(s):	Millner; Alan (Lexington, MA), Mongeau; Peter P. (Westborough, MA), Daboussi; Zaher (Boylston, MA)
Assignee:	Kaman Electromagnetics Corporation (Hudson, MA)
Application Number:	07/931,196
Patent Claims:	1. A four quadrant unipolar pulse width modulated (PWM) power conversion circuit for supplying a desired current to an inductive load and for maintaining the desired current within a bandgap defined by adding a predetermined offset current magnitude to the desired current magnitude to define an upper boundary current magnitude and subtracting said predetermined offset current magnitude from the desired current magnitude to define a lower boundary of the gap, said circuit comprising: an H-bridge circuit topology having: an upper pair of switching elements and a lower pair of switching elements, a first upper switching element S1 coupling a first terminal of said load to a positive potential of a DC power source and a second upper switching element S3 coupling a second terminal of said load to said load to said positive potential of said power source; a first lower switching element S4 coupling said first terminal of said load to a negative potential of a DC power source and a second lower switching element S2 coupling said second terminal of said load to said negative potential of said power source; first diode means in parallel with said first upper switching element S1 and having its anode terminal connected to said first terminal of said load and its cathode terminal connected to said DC power source positive potential; second diode means in parallel with said second upper switching element S3 and having its anode terminal connected to said second terminal of said load and its cathode terminal connected to said DC power source positive potential; third diode means in parallel with said first lower switching element S4 and having its cathode terminal connected to said first terminal of said load and its anode terminal connected to said DC power source negative potential; fourth diode means in parallel with said second lower switching element S2 and having its cathode terminal connected to said second terminal of said load and its anode terminal connected to said DC power source negative potential; a means for generating a first set of timing pulses defined as CLOCK A with each pulse corresponding to a logical 1; a means for generating a second set of timing pulses defined as CLOCK B with each pulse corresponding to a logical 1 and each pulse shifted 180 degrees with respect to the timing pulses of said CLOCK A; current sensing means serially connected to said load for generating signals indicative of the magnitude and direction of the current flowing through said load; means for logically deriving signals indicative of a voltage imposed across said load; means for generating signals indicative of a comparison of the sensed load current signals with signals indicative of the desired load current, and control means electrically coupled to said switching elements S1-S4 and receiving said timing pulses, said load voltage signals and said load comparison signals, said control means including means for generating a first set of switching element control signals to cause said first upper switching element S1 and said second lower switching element S2 to become conductive to provide a current path through said load in a first direction; a second set of switching element control signals to cause said second upper switching element S3 and said first lower switching element S4 to become conductive to provide a current path through said load in a second direction; a third set of switching element control signals to cause said first and second switching elements to become conductive to create a short circuit across said load by creating a current path from said positive potential through said conductive one of said first and second upper switching elements through said load, through said respective diode means in parallel with the non-conductive one of said first and second upper switching elements, said diodes being forward biased to return to said positive potential, and a fourth set of switching element control signals to cause one of said first and second lower switching elements to become conductive to create a short circuit across said load by creating a current path from said negative potential through said conductive one of said first and second lower switching elements, through said load, through said respective diode means in parallel with the non-conductive one of said first and second lower switching elements, said diode means being forward biased to return to said negative potential, said switching element control signal sets to selectively operate each of said switching elements S1-S4 between a conducting (logical 1 or high) and a nonconducting (logical 0 or low) state; said control means further comprising an active current controller for selecting a one of said control signal sets and setting the state of each of said switching elements S1-S4, respectively, given by the following expressions: S1=IPOL*(DIR*VMODE+OA*(DIR+VMODE)); S2=IPOL*(DIR*VMODE+OA*(DIR+VMODE)); S3=IPOL*((DIR*VMODE+OA*(DIR+VMODE))); S4=IPOL*((DIR*VMODE+OA*(DIR+VMODE))); wherein DIR=1 corresponds to increasing magnitude load current and DIR=0 to decreasing magnitude load current, IPOL=1 corresponds to a positive load current and IPOL=0 corresponds to a negative load current, OA=1 corresponds to an electrical short of said load with switching elements S1 and S3 operated and OA=0 corresponds to an electrical short of said load with switching elements S2 and S4 operated, such that the current through the load is changed to decrease in magnitude if rising and either the upper boundary is reached or CLOCK B=1 and changed to increase in magnitude if decreasing and either the lower boundary is reached or CLOCK A=1, and wherein VMODE=1 corresponds to a positive voltage polarity impressed across the load and VMODE=0 corresponds to a negative voltage polarity impressed across the load such that the voltage across the load is changed to a positive polarity if the lower current boundary is reached and CLOCK B=1 and is changed to a negative polarity if the upper current boundary is reached and CLOCK A=1, thereby causing the instantaneous voltage across the load to alternate between a single polarity voltage and zero for a portion of the output waveform across said load to cause said average value of said load current to correspond generally with said desired average load current. 2. A four quadrant unipolar PWM power conversion circuit as defined in claim 1 further comprising said control means generating a fifth set of switching element control signals to cause said second upper switching element S3 and said first lower switching element S4 to become conductive to provide a current path through said load in a second direction opposite to said first direction. 3. A four quadrant unipolar PWM power conversion circuit as defined in claim 1 wherein said control means activates said switching elements in sequence wherein said third and fourth set of switching element control signals are alternately applied with respect to one another and one or the other of said third and fourth set of controls signals is applied each time said first set of switching element control signals are applied to distribute substantially evenly among said switching elements the dissipation of heat generated due to switch transitions. 4. A four quadrant unipolar PWM power conversion circuit as defined in claim 1 further including said PWM power conversion circuit operating in a fixed frequency pulse width modulated mode. 5. A four quadrant unipolar PWM power conversion circuit as defined in claim 1 wherein said instantaneous load voltage automatically shifts from a first single polarity voltage to a second single polarity voltage in response to a control signal representative of the difference between the value of said desired average load current and said actual average load current. 6. A four quadrant unipolar PWM power conversion circuit as defined in claim 1 wherein said switching element control signals are input through corresponding enable latches to prevent unintentional state transitions of said first and second upper switching elements S1 and S3 and said first and second lower switching elements S2 and S4, respectively.

Details for Patent 5,428,522

Applicant	Tradename	Biologic Ingredient	Dosage Form	BLA	Approval Date	Patent No.	Expiredate
Sanofi Pasteur Sa	IPOL	poliovirus vaccine inactivated	Injection	103930	February 04, 2000	5,428,522	2040-01-29